1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly relates to a semiconductor memory device that can relieve bit defects generated sporadically.
2. Description of Related Art
Memory capacities of semiconductor memory devices such as DRAM (Dynamic Random Access Memory) have been increased year by year according to improvements in microfabrication technology. However, as downscaling of semiconductor memory devices improves, the number of defective memory cells per chip has been increased. Such defective memory cells are replaced by redundant memory cells, so that defective addresses are relieved.
Normally, defective addresses are stored in a fuse circuit including a plurality of program fuses and when an access to a corresponding address is requested, not a defective memory cell but a redundant memory cell is accessed by the control of the fuse circuit. The defective addresses are detected in screening tests performed in a wafer state, and a laser beam is irradiated according to the detected defective addresses, thereby the program fuses are cut.
However, even after performing such address replacement, defective bits may be generated sporadically due to thermal stresses during packaging, for example. When defective bits are found after packaging, the address replacement using laser beam irradiation cannot be performed and thus the defective devices have to be handled as defective products.
As a method for solving such a problem, there has been proposed a method of providing a defect relief circuit capable of relieving a small number of defective bits found after packaging in addition to address replacement utilizing laser beam irradiation. With this method, as for the circuit that stores defective addresses, not a fuse circuit requiring laser beam irradiation but an electrically writable non-volatile memory circuit is used. For such a memory circuit, a so-called “anti-fuse circuit” that utilizes dielectric breakdown of oxide films can be used.
The number of defective bits found after packaging is much smaller than the number of defective bits found during a selection test. Therefore, not word line-by-word line or bit line-by-bit line basis replacement but bit-by-bit replacement is preferably performed. Devices described in Japanese Patent Application Laid-open Nos. 2002-298596, 2008-71407, 2004-158069, and 2006-268970 are known as a semiconductor memory device capable of relieving sporadic bit defects.
The semiconductor memory device described in Japanese Patent Application Laid-open No. 2002-298596 is a DRAM, and relief storage cells formed of SRAM cells are arranged in a sense amplifier array included in a memory cell array, thereby relieving sporadic bit defects.
The semiconductor memory device described in Japanese Patent Application Laid-open No. 2008-71407 is also a DRAM, and a relief storage cell is connected to an output terminal of a read amplifier and an input terminal of a write amplifier, thereby relieving sporadic bit defects.
In Japanese Patent Application Laid-open No. 2008-71407, a relief circuit is arranged to be in parallel with a main amplifier (150) that reads data of a regular memory cell (110) in a preceding stage of an input/output circuit (FIFO circuit) connected to an external data terminal (FIG. 1). Further, the relief circuit is arranged to be in parallel with a write amplifier WB that writes data in the regular memory cell (110) (FIG. 3).
In Japanese Patent Application Laid-open No. 2004-158069, a relief circuit is arranged in a LOGIC macro outside a DRAM macro (FIG. 2) to be in parallel with an input/output bus (MUXOUT) between a DRAM macro and the LOGIC macro via a selector (FIG. 3).
In Japanese Patent Application Laid-open No. 2006-268970, a first relief bit register is arranged to be in parallel with a first read/write amplifier through a read/write bus connected to a DQ input/output buffer circuit.
However, because a relief storage cell is arranged in a sense amplifier array in the semiconductor memory device described in Japanese Patent Application Laid-open No. 2002-298596, a line-and-space value (L/S) for a transistor, a wiring, and a contact that constitute a relief storage cell has to coincide with a line-and-space value (L/S) for a transistor, a wiring, and a contact that constitute a sense amplifier to prevent an increase in the area of the memory cell array. Accordingly, the possibility that defects occur in the relief storage cell itself is increased. To relieve defects occurred in the relief storage cell, I/O redundant circuits can be used. However, causing defects in the circuit itself provided for relieving sporadic defective bits and increasing I/O buses to relieve such defects are not realistic.
Further, in the semiconductor memory device described in Japanese Patent Application Laid-open No. 2002-298596, because a relief storage cell is arranged within a memory cell array, a distance between a main amplifier (a circuit including a read amplifier and a write amplifier) and the relief storage cell is significantly extended depending on a position of a memory block. Respective distances from the main amplifier to the relief storage cells sporadically present in the memory block vary significantly. As a result, read margins and write margins of the respective relief storage cells are different from each other from view of the main amplifier, and thus a timing of operating of the main amplifier and the relief storage cell has to be changed depending on the position of the memory block. This complicates control of the device significantly.
Moreover, in the semiconductor memory device described in Japanese Patent Application Laid-open No. 2002-298596, the distance from a main amplifier to a relief storage cell is extended. Thus, when a sense amplifier is to be connected to the main amplifier by a hierarchized data bus (for example, a lower local I/O line and a higher main I/O line), contact resistances between multi-hierarchies deteriorate a time constant of the hierarchized data bus with large parasitic capacitance. As a result, a difference in access margin depending on the position of the memory block becomes further significant.
According to the semiconductor memory device described in Japanese Patent Application Laid-open No. 2008-71407, the relief storage cell is connected to an output terminal of a read amplifier and an input terminal of a write amplifier. Therefore, the number of components required for connecting to a relief storage cell is large and thus control of the device becomes complicated.